Byte Blaster Clone for use in Quartus - del90003
Programming an FPGA or CPLD by Parallel Port is
possible with appropriate Interface Circuit and
cable. Here is an example for loading bytes into an
- FPGA CPLD Structured ASIC
A project in elektor electronics - elektor.de
got me interested in this. You can try the Quartus
Edition, and learn some basics of CPLD and
FPGA, This page is intended for that..
"The ByteBlastera parallel port download cable is a
hardware interface to a standard PC parallel port
(also known as an LPT port). This cable channels
configuration data to FLEX 10K, FLEX 8000, and FLEX
6000 devices, as well as programming data to MAX
9000, MAX 7000S, and MAX 7000A devices. Because
changes are downloaded directly to the device,
prototyping is easy and multiple design iterations
can be accomplished in quick succession
Loomis – Computing and Engineering
The ByteBlaster cable has a 25-pin male header that
connects to the PC parallel port, and a 10-pin
female plug that connects to the circuit board. Data
is downloaded from the PCs parallel port through the
download cable to the circuit board via the
The circuit below is the Byte Blaster Schematic. The
clone circuit drawn by me is shown far below too.
Clone for use in Quartus - del90003
view circuit click the Link of PNG or PDF, The PNG
Image can be Drag Scrolled with Mouse.
contain an array of programmable logic blocks,
and a hierarchy of reconfigurable interconnects that
allow the blocks to be "wired together", like many
logic gates that can be inter-wired in different
Logic blocks can be configured to perform complex
combinational functions, or merely simple logic
gates like AND and XOR. In most FPGAs, logic blocks
also include memory elements, which may be simple
flip-flops or more complete blocks of memory.
Learn more on fpga here fpga4fun.
Learn more about Programmable Logic Devices -PLD SS-MAG-PLD.
ByteBlaster PDF. Have a look at some projects
Connect this circuit to printer port with a good
quality shielded cable. The design source is a
zip file 90003.zip
unzip and open in Orcad Capture to edit
Stratix IV FPGA from Altera